Strong knowledge of design verification methodologies and experience with simulation tools generating FSDB outputs.
Proficient in analyzing FSDB files to extract and interpret signal performance data for complex SoC designs.
Skilled in scripting and automation (e.g., Python) to process and visualize FSDB data efficiently.
Able to work autonomously and drive progress with minimal supervision.
Create and maintain UVM-based test benches for IP and SoC verification
Experience in AXI, DDR protocols and performance testing
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